The present invention relates to a semiconductor device and a memory access control method, and relates to the technology of storing data and an error detecting code generated from the data in a memory, for example.
Patent Literature 1 discloses a memory control circuit as an example in the past as illustrated in FIG. 4 of the Patent Literature 1. This memory control circuit includes an address/control-line controlling circuit and an ECC circuit. When an address and data are sent to the memory control circuit from a CPU, the ECC circuit generates ECC data from the data and writes it at a specified address of the memory. When reading data, the ECC circuit creates new ECC data from the data read from the memory, compares the ECC data read from the memory with the newly created ECC data, and makes the error detection and the correction of the data.
However, in this memory control circuit, there is a problem that it is difficult to detect an address error at the time of occurrence of a fault of the value sticking, in any one of the address signal lines which the address/control-line controlling circuit uses to specify the address to the memory. This is because the data and the ECC data created from the data are to be written at the address specified to the memory; accordingly, even if the data and the ECC data are read from an address different from expectation, no disagreement will be detected in comparing the read ECC data with the newly created ECC data.
Here, in order to solve this problem, a computer system disclosed by Patent Literature 1 specifies separately the address to write the data and the address to write the ECC data. However, this technology is completely different from the technology to be disclosed by the present specification in solving the above problem.
(Patent Literature 1) Japanese Unexamined Patent Application Publication No. Hei 5 (1993)-88992.